1. Field of the Invention
The invention relates generally to a Synchronous Dynamic Random Access Memory (SDRAM) and more particularly to a dual address decoding scheme for accessing two I/O locations in one cycle of a Double Data Rate (DDR) SDRAM.
2. Description of the Related Art
Semiconductor memories frequently access data in blocks, where the block length or burst is variable. The access to storage can be sequential or interleaved and affects the memory address sequence as shown in TABLE 1. For a traditional semiconductor memory the address supplied is a system responsibility. The supplied address typically is decoded by the memory to a single column or to a block address to read or write data into memory, e.g. a three bit address may provide a pre-decode of one of 8 columns from say S0 to S7. Such a simple decoding circuit for a three bit pre-decoder is shown in FIG. 1. To access redundant columns, provided in virtually all solid state memories to ensure an adequate yield in the manufacturing process, special addressing circuits are provided which consist of circuits with `fuses` which can be blown to define and store the defective address in the fuse memory.
TABLE 1 ______________________________________ block addressing: Starting Burst Column Order of Access within a Burst Length Address Type = Sequential Type = Intervleaved ______________________________________ 2 A0 0 0-1 0-1 1 1-0 1-0 4 A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 8 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Full n = A0-A7 Cn, Cn + 1, Cn + 2 Not supported Page (location 0-255) Cn + 3, Cn + 4 . . . (256) . . . Cn - 1, (Cn + 256), Cn, (Cn + 257) . . . ______________________________________
Such a circuit is shown in FIG. 2. The operating principle of this circuit is as follows. If the combination of fuse path and N-channel Metal Oxide Semiconductor (NMOS) devices, controlled by the input address, is no DC path from line HIT to ground, then the line HIT will be pulled up by the p-channel metal oxide semiconductor (PMOS) device and kept at high level. This state of the match circuit is defined as the `active` state. The active state of the match circuit will enable one column redundancy. But if any direct current (DC) path exists (a combination of fuse path and NMOS device) in this match circuit, then the line HIT will be pulled down through this DC path and be kept at ground level. This state of the circuit is the `inactive` state.
Referring again to FIG. 2, we now describe the match circuit in more detail. The circuit is made up of a gating and a fuse section. The gating section consists of p-channel transistors P2 and P3 and n-channel transistors N20, N21, and N22. Transistors P2 and P3 are connected in series between the positive power supply 28 and the drains of transistors N20 and N21. The sources of N20 and N21 are connected to the reference voltage 29. Input SELB, the inverse of SEL, is connected to the gates of P2 and N20. Input SEL connects to enable-fuse 18. Enable-fuse 18 when blown enables the match circuit. The other end of enable-fuse 18 connects to the gates of P3 and N21 and to the drain of N22. The gate of N22 is tied to the positive power supply 28, while the source of N22 is connected to the reference voltage 29. When enable-fuse 18 is blown and when SEL is active (logical 1), line HIT is ready to be activated by the combination of input address and depending if a match-fuse 10 to 17 of the upper fuse section 201 or a match-fuse 10B to 17B of the lower fuse section 202 is blown or not.
Still referring to FIG. 2, the fuse section will be explained next. The fuse section comprises an upper and lower fuse section 201 and 202, respectively. Each fuse section consists of a group of seven strings, each string made up of a serial connection comprising a match-fuse and an n-channel transistor. As just mentioned the upper match fuses are labeled from 10 to 17 and the lower match-fuses are labeled from 10B to 17B. These match-fuses are used to match the address of a failing column e.g. S0 to S7. One end of each fuse is connected to line HIT. The other end of each fuse is connected to the drain of the n-channel transistor, and the source of each transistor is connected to the reference voltage 29. The gates of the eight transistors of the upper group are connected to address lines B0, B1, B2, B3, B4, B5, B6, and B7, respectively. The gates of the eight transistors of the lower group are connected to address lines B0B, B1B, B2B, B3B, B4B, B5B, B6B, and B7B, respectively. The suffix `B` implies that these lines are the logical inverse of the address lines of the upper group. Inverter 23 is connected between line HIT and output HITB.
Of related art patents, U.S. Pat. No. 5,663,924 (Barth, Jr. et al.) provides an SDRAM with a boundary-independent block decoder, which can provide data in various burst lengths and in both interleaved and sequential modes. U.S. Pat. No. 5,610,874 (Park et al.) describes an address decoder for an SDRAM optimized for a fast burst mode operation. U.S. Pat. No. 5,629,903 (Agata) discloses an address decoder for an SDRAM having pre-decoders for fast column-select line activation.